The present disclosure relates generally to a display port link between a processor and a display device. More specifically, the present disclosure relates to reducing a number of cables used in the display port link between the processor and the display device using a link aggregator.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Generally, image data to be depicted on a display device may be transmitted from a processor to a display device via a cable bundle that includes a number of micro-coaxial (μ-coax) cables. In a laptop platform, for example, the cable bundle may pass from an Embedded DisplayPort (eDP) connector located on a motherboard, through a clutch barrel, to an eDP connector located on the display device. To display the image data provided by the processor located on the motherboard, the clutch barrel may be large enough to house the cable bundle, such that the cable bundle is routed between the motherboard and the display device. As such, the number of micro-coaxial cables in the cable bundle may affect how the clutch barrel should be sized, what components may be housed by the clutch barrel, and the like. To use more aggressive (i.e., smaller) form factor designs in laptops and other computing devices, it may be beneficial to reduce the number of cables used in the cable bundle to send image data from the processor located in the motherboard to the display device.